nMOS Transistor ( With Ultra-low Power Consumption, Energy-efficient Computing, During The Sub-Threshold Range)

Note: nMOS field effect tunnel transistor  is an experimental type of transistor.   Even  though its structure is very similar to an nMOS- oxide semiconductor field-effect transistor  , the basic switching mechanism  in  these two  transistors   is different . Modulation of quantum tunneling  through a switch barrier.

nMOS field-effect tunneling transistor  , as an alternative to conventional CMOS by enabling voltage supply (VDD) with ultra-low power consumption, energy-efficient calculations, during the sub-threshold slope range: SS) was born. That type of device is a gated reverse bias structure, which is usually called an  nMOS tunnel field effect transistor  . For low power applications,  nMOS  is considered. This device has less static leakage current than MOSFET and is more resistant to SCEs.

The most prominent feature of  nMOSs  is  the capacity to produce a reverse sub-threshold swing (SS) less than 60 mV/decade of the thermal limit (at 300 K) of  conventional reverse mode nMOSs . Quasi-thermal ss is achievable because the drain current in  nMOSs  is generated by carrier injection from the source to the channel, which often falls under the quantum mechanical band-to-band tunneling (BTBT) radius.

The speed of the nMOS transistor   is proportional to the current. The higher the current, the faster the transistor will be able to boost and charge (sequential capacitor voltage).  For a given transistor speed and maximum acceptable subthreshold leakage, the subthreshold slope thus specifies a minimum threshold voltage.  Reducing the threshold voltage is an essential part of the idea for scaling  the nMOS constant  . To overcome some challenges associated with  peripheral nMOS structures  , such as their need for ultra-sharp doping profiles;  However, such devices   may suffer from gate leakage  due to the presence of large vertical fields in the nMOS transistor structure.