Binary implementation of parallel ternary full adder and subtractor

In this paper a binary design for ternary base 3 adder and subtractor which are the main part of ternary ALU's in optical and quantum computers is presented. The cost functions of computation in different radices are calculated and the optimum radix is selected for design.

کلیدواژه ها:

base ، FPGA ، qudit ، radix ، trit ، verilog