Reduced Complexity Architecture for Integral Image Generation

Integral image plays an important role in AdaBoost algorithm which uses Haar-like features. The calculation of integral image needs many accesses to memory and most of the required addresses are not sequential. In addition, its calculation is compute-intensive. In this paper we propose an approach for generating integral image to cope with nonesequential addresses by affine transforming input image and using a pipeline architecture to compute results in an improved way. This approach needs the lowest clock pulses for integral image generation and in addition, its architecture is improved and less complex

کلیدواژه ها:

integral image ، generation ، architecture ، pipeline ،