A Novel Soft Error Hardened 14T SRAM Cell

Technology scaling has brought forth major issues related to process variation such as circuit stability and reliability degradation, which are especially problematic for the Static Random Access Memories (SRAM). As we know SRAM occupies the majority of the die area in system-on-chips and microprocessors. Because of Low operating voltage, small node capacitance, high packing density, and lack of error masking mechanisms memories are more vulnerable to soft error.This paper propose a new hardening design for an 14 transistors (14T) cmos memory cell at 32nm feature size.the proposed hardened memory cell overcome the circuit stability problem of previous design by utilizing separate bit lines for read and write operation. The simulation results show that the 14T cell has better stability and lower power consumption in compare to recent reported designs. In addition the proposed cell exhibits 36% larger critical charge than the conventional design

کلیدواژه ها:

Soft Error ، SRAM Hardened ، Nano technology