Improving Efficiency and Reducing Clock Speed RequirementSimultaneously in Delta Sigma Modulator Transmitter

This paper introduces an architecture to enhance efficiency and reduce clock speed requirement of the Delta–Sigma Modulator (DSM)–transmitters. For this purpose, the quantization noise reduction technique and timeinterleavedparallel DSM are used. By using this combined technique with four-branch time-interleaved DSM for anlong-term evolution (LTE) signal with ۱.۹۲ MHz bandwidth, ۷.۸ dB peak to average power ratio (PAPR) and anoversampling ratio (OSR) of ۱۶, the coding efficiency (CE) of transmitter is improved from ۹.۷% to ۲۲.۳% with ۴۲dBsignal to noise and distortion ratio (SNDR) while the clock speed is only ۷.۶۸ MHz. it is four times lower than the clockspeed requirement of conventional DSM to achieve the same SNDR.

کلیدواژه ها:

Delta–sigma modulator (DSM) ، long-term evolution (LTE) ، coding efficiency (CE) ، signal to noise and distortionratio (SNDR) ، power amplifier (PA).