Performance Enhancement in a Two-Stage Amplifier with Positive Capacitive Feedback Compensation

This paper presents a two-stage amplifier with positive capacitive feedback compensation and enhanced performance in 0.18μm CMOS process. In this type of amplifier, unlike the Miller compensated two-stage amplifiers, dominant pole is located at the output of the amplifier. So, phase margin (PM) improves if the capacitive load is increased. Effect of the non-dominant pole is reduced by the left half plane zero, which is introduced by the positive capacitive feedback network. In this work, higher gain bandwidth (GBW), higher slew rate, and also higher common mode rejection ratio (CMRR) are achieved, by using a new structure. The proposed amplifier improves low frequency CMRR by 530% (16dB), slew rate by 50% and GBW by 47.3%. For 1.8V supply voltage, DC gain and power consumption are 83.7dB and 880μw, respectively. Also, low frequency CMRR and power supply rejection ratio are 143 and 84.7dB, respectively. GBW, PM, and slew rate for a 5pF capacitive load are 131MHz, 62.3°, and 13 V/μs, respectively. Moreover, 0.1% settling accuracy for a 0.5v input signal in unity gain configuration is 47ns.

کلیدواژه ها:

Amplifier ، high gain ، positive capacitive feedback compensation ، CMRR ، PSRR ،