Low Settling Time All Digital DLL for VHF Application
محل انتشار: ماهنامه بین المللی مهندسی، دوره: 28، شماره: 3
سال انتشار: 1393
نوع سند: مقاله ژورنالی
زبان: انگلیسی
مشاهده: 522
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شناسه ملی سند علمی:
JR_IJE-28-3_011
تاریخ نمایه سازی: 4 خرداد 1395
چکیده مقاله:
Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) are commonly used as a synthesizer orclock and data recovery circuit in most of the communication systems. In this paper, a new DLL isdesigned based on PRP conjugate gradient algorithm. The proposed DLL do not need any phasefrequency detector, charge pump and loop filters, hence it can contribute better jitter performance andhigher speed in comparison with conventional DLLs. In this design, PRP conjugate gradient algorithm isused to optimize the delay amount of each delay cells therefore helps the DLL to lock more accuratelyand quickly compared with gradient algorithm. In addition, for applying the PRP conjugate gradientalgorithm a digital signal processor is used in the proposed architecture. To show the accuracy of theproposed structure’s operation, simulation has been done for 15 delay cells and fREF is chosen 14MHz tohave output frequency 14×15=210MHz. fOUT=210 MHz is one of the channels in Iran VHF frequencyband. As shown with simulation, the proposed architecture has a locking time of approximately 286nsecwhich is equal to 4 clock cycles of the reference clock.
کلیدواژه ها:
DLLDelay Locked Loop PRPConjugate GradientAlgorithmSynthesizer
نویسندگان
H. Rahimpoura
Department of Electrical Engineering, University of Tehran, Iran
M. Gholami
Department of Electrical and Electronic Engineering, University of Mazandaran, Iran
G Ardeshirc
Department of Electrical and Computer Engineering, BabolNoshirvani University of Technology, Iran
H MiarNaimic
Department of Electrical and Computer Engineering, BabolNoshirvani University of Technology, Iran