Efficient Comparator Design: Rail-to-Rail, ۰.۶V, ۲۷۰fJ, ۵۰۰nW Comparator in ۱۸۰nm CMOS Technology

Amidst the rising efficiency of digital signal processors, the demand for analog-to-digital converters (ADCs) boasting low power consumption and high precision has surged. It is crucial to create a functionally optimum comparator because of the multiplicity of parameters included in the comparator. In this paper, we introduce a rail-to-rail comparator operating at sub-۱V levels with nanowatt power consumption. Our proposed design leverages innovative techniques, such as input to the bulk and gate connection to ground, harnessing the transistor's body transconductance. Implemented in ۰.۱۸ µm CMOS technology with a ۰.۶V power supply using HSPICE software, our suggested comparator has an EPC of ۲۷۰fJ and a power consumption of around ۵۰۰ nanowatts. Furthermore, we simulate the comparator in the corner case. Finally, a comparison of the suggested comparator's power consumption, power supply, and operating frequency is made with dynamic comparators.

کلیدواژه ها:

Low power consumption ، Rail-to-rail ، Sub-۱V ، Energy per Conversion (EPC)