High Speed Delay-Locked Loop for Multiple Clock Phase Generation

سال انتشار: 1392
نوع سند: مقاله ژورنالی
زبان: انگلیسی
مشاهده: 845

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شناسه ملی سند علمی:

JR_JECEI-1-1_003

تاریخ نمایه سازی: 27 فروردین 1393

چکیده مقاله:

In this paper, a high speed delay-locked loop (DLL) architecture is presented which can be employed in high frequency applications. In orderto design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which can be triggered bydouble edges of the input signals. In addition, the blind zone is removeddue to the elimination of reset signal. Therefore, operating frequency ofthe whole system is improved which can be mentioned as notable advantage of the proposed DLL. To obtain more accurate phases at the output signal, a new delay cell is introduced which is controlled by a single voltage. This control voltage, through equalizing the rise and fall time, regulate duty cycle of output clock. These features along with simplicity and low power consumption qualify the proposed architecture to be widely used in high speed systems. For better realization of the designed circuit’s behavior, simulation results are presented based on TSMC 0.35μm CMOS technology and 3.3-V power supply for a type II filter which demonstrate accuracy and perfect performance of this work.

کلیدواژه ها:

Delay locked loop (DLL) Phase detector (PD) Charge pump (CP) Filter CMOS

نویسندگان

A Ghanbari

Graduate School of Electrical Engineering, Qazvin Islamic Azad University (QIAU), Qazvin, Iran

A Sadr

Department of Electrical Engineering, Iran University of Science and Technology (IUST), Tehran, Iran

M Nikoo

Department of Computer and Electrical Engineering, Islamic Azad University (MIAU)