An Ultra Low Power-Delay-Product 1-bit Full Adder Design

The general goal of our work is to reduce power-delay-product (PDP). In this paper a new full adder cell based on modified two stage XOR gate andmajority function that use as MOS capacitor (MOSCAP). We produce carry and sum at the same time with two different circuits. Our new full adderhas been contrasted with following full adders: Conventional CMOS full adder, Complementary Pass Logic, Transmission Gate Adder and MajorityFunction based full adder. This full adder simulated on HSPICE with 0.18μm TSMC. New combination full adder has more than 22% in power saving over a majority function-based one bit full adder

کلیدواژه ها:

Full adder ، low power ، XOR gate ، Majority Function ، MOSCAP