Carbon Nano Tube Ternary Galois Field: A Building Block for Nano Scale Computing

Carbon nanotubes (CNT) discovered in 1991 by Iijima are a fascinating new class of materials from both theoretical and applied standpoints. Their unique properties have sparked new research areas in physics, chemistry, materials science and electronics. The growth of technology and the fast improvements of CMOS circuit scaling has led to more integrated computer circuits. As the electronic circuits keep shrinking, we are moving fast to the point that further miniaturization of silicon based circuits is impossible due to the physical limitations. Carbon nanotube studies have revealed the unique morphologies and special characteristics of CNT such as: the relatively small dimensions, high mobility of electrons, ballistic transport and high Ion-Ioff ratio [1, 2]. Thus CNTFETs have been suggested as an appropriate successor to silicon MOSFETs.As a scaling limitation, the threshold voltage can not be decreased deliberately. But in CNTFETs due to the fact that threshold voltage is in reverse proportion with the nanotube diameter [3], different threshold voltages can be obtained simply by defining different nanotube diameters. This feature of carbon nanotubes has been exploited in implementation of multiple valued logic (MVL) circuits. Multiple valued logic makes it possible to implement mathematical functions with fewer operations [4]. Moreover it is capable of reducing the area consumption and solving the complexity of interconnection problem, as the number of lines needed for data transfer in MVL is less than in binary logic. In MVL, there have been many ways suggested to represent the logical functions in canonical form and to simplify them. One of the frequently practiced methods is using the three operators min,tsum and literal, which makes a functionally complete set and accordingly every MVL function can be represented using them.This paper proposes a novel design for Galois field that incorporates the advantages of both CNTFETs and three valued logic. The number of transistors and resistors in the proposed design is reduced compared to the design which uses three MVL basic operators: min,tsum and literal