Implementation Of Low Power Floating Point Adder On FPGA

An efficient design of floating-point adder onto an FPGA offers major area and performance overheads. With the recent advancement in FPGA architecture and area density, latency has been the main focus of attention in order to improve performance. Our research was oriented towards studying and implementing tandard, Leading One Predictor(LOP), and far and close data-path floating-point addition algorithms. Each algorithm has complex sub-operations which lead significantly to overall latency of the design. Each of the suboperationis researched for different implementations and then synthesized onto a STRATIX II FPGA device to be chosen for best performance. Our implementation of the standard algorithm occupied 420 slices and had an overall delay of 28 ns. The standard algorithm was pipelined into five stages to run at 120 MHz which took an area of 324 slices and power is 35mw.

کلیدواژه ها:

Floating Point Adder ، FPGA ، Single Precision