DTM and DVFS Techniques for the mSWNoC Architecture

Traditional multi-core designs, based on the Network-on-Chip (NoC) paradigm, suffer from high latency and power dissipation as the system size scales up due to the inherent multi-hop nature of communication. Introducing long-range, low power, and high-bandwidth, single-hop links between far apart cores can significantly enhance the performance of NoC fabrics. The mm-wave small-world wireless NoC (mSWNoC) has emerged as an enabling interconnection infrastructure to design high-bandwidth and energy-efficient multicore chips. In this mSWNoC architecture, long-range communication predominately takes place through the wireless shortcuts operating in the range of 10-100 GHz, whereas the short-range data exchange occurs through conventional metal wires.This results in performance advantages (lower latency and energy dissipation) mainly stemming from using the wireless links as long-range shortcuts between far apart cores. The performance gain introduced by the wireless channels can be enhanced further if the wireline links of the mSWNoC are optimized according to the traffic patterns arising out of the application workloads. The article focuses on power and thermal management strategies to enhance NoC sustainability. As hundreds of cores are integrated in a single chip, designing effective packages for dissipating maximum heat is infeasible. Moreover, technology scaling is pushing the limits of affordable temperatures. Thus, addressing thermal concerns at different design stages is critical to the success of future generation systems. In this context, Dynamic Thermal Management (DTM) and Dynamic Voltage and Frequency Scaling (DVFS) appears solutions to avoid high spatial and temporal temperature variations among NoC components, and thereby mitigate local network hotspots.

کلیدواژه ها:

Network-on-Chip (NoC) Paradigm ، mSWNoC Architecture ، Dynamic Voltage and Frequency Scaling (DVFS) ، Dynamic Thermal Management (DTM)