Delay Model Estimation in RC-tree Circuits Based on the Power lognormal Distribution

Computation of the second order delay in RC-tree based circuits is important during the design process of modern VLSI systems with respect to having tree structure circuits. Calculation of the second and higher order moments is possible in tree based networks. Because of the closed form solution, computation speed and the ease of using the performance optimization in VLSI design methods such as floor planning, placement and routing, the Elmore delay metric is widely implemented for past generation circuits. However, physical and logical synthesis optimizations require fast and accurate analysis techniques of the RC networks. Elmore first proposed matching circuit moments to a probability density function (PDF), which led to the widespread implementation of it in many networks. But the accuracy of Elmore metric is sometimes unacceptable for the RC interconnect problems in today’s CMOS technologies. The main idea behind our approach is based on the moment matching technique with the power-lognormal distribution and proposing the closed form formula for the delay evaluation of the RC-tree networks. The primary advantages of our approach over the past proposed metrics are the ease of implementation, reduction of the complexity and proposing an efficiency formula without referring to lookup tables. Simulation results confirmed that our method illustrates a good degree of accuracy and the relative average of errors is less than 20%.

کلیدواژه ها:

Power-lognormal distribution ، Elmore delay ، Circuit analysis ، Physical synthesis ، Moment matching ، Simulation