New method in FPGA implementation of AES algorithm

NIST has announced Rijndeal as Advanced Encryption Standard (AES) in October 2nd 2000. Before that, DES was used, which was invalid because of imperfection and fault at the time of invasions. AES is a symmetric parochialalgorithm code. There are 3 different architectures for coding and decoding the 128bit data using AES algorithm. Coding and decoding units have aprocessing unit key beside them in addition to data processing unit, which produce under-keys at the same time of processing. The first one is calledrepetitive basic AES which uses a set of hardware constitutively in order to process 10 procedures. The second is one-stage outer pipeline in parish. These two architectures were synthesized and produced in Spartan-3 as FPGA parts. Basic repetitive AES coder, codes data in 1.3Gbit/s and one-stage pipeline codes them in 2.3 Gbit/s. The 3rd architecture is a developed type of one stage pipeline into a 4 level pipelines. This architecture was produced in Virtex4, as a Xilinx family. Advantage of use increased up to 14.3Gbit/s. In addition, by the first and second architectures synthesizing in this hardware, 2.8Gbit/s and 5.8Gbit/s advantages of use have been reached.

کلیدواژه ها:

AES ، Coding ، Cryptography ، Decoding ، FPGA