FPGA Implementation of Multiplier less FIR Filter in Hearing Aids

Design a FIR filter with low complexity is one of the main issue in signal processing and is generally higher than that of a corresponding infinite-impulse response (IIR) filter meeting the same magnitude response specifications. The complexity (in terms of the implementation cost in VLSI) of an FIR filter is dominated by the multiplication of a large number of filter coefficients by the filter input or its time-shifted versions. During the past decades, continuous effort has been made to design low complexity FIR filters. One of the most successful strategies for optimizing filter coefficients, is Signed Power-of-Two (SPT) space. Where each coefficients is displayed as a sum of a limited number of SPT terms. Can be replaced by shifters and adders, so that the implementation of the filter is essentially multiplier less. Total number of adder in FIR filters for implementation can be much more reduced by extracting common sub expression from coefficients. In this paper we implement this technique in FPGA SPRTAN 3E and show this reduction in the computational complexity.

کلیدواژه های FPGA Implementation of Multiplier less FIR Filter in Hearing Aids:

Computational complexity ، SPT term ، Multiplier less FIR ، sub expression