Simulation of Hardened D-Latch Circuit in Carbon Nanotubes Technology

Today, by the decrease of the size of transistor in CMOS Technology, there is an increase in the sensitivity and vulnerability of the integrated circuits against single-event upsets, which are due to collision of high-energy particles in flip-flop system. In this paper, in order to design a hardened D-Latch circuit, transistors which are based on carbon nanotubes are used. Also, in order to retrofit memory cells against transient fault, Dual Interlock Cell (DICE) is used to reduce the critical charge among sensitive nodes. In this paper, the suggested circuit is simulated using HSPICE simulator and CNTFET transistor model, which is proposed in 2008 by Stanford University and includes a library of physical and electrical parameters of CNTFET transistors. Then, this circuit is compared in term of critical charge, with the circuit which is designed in CMOS technology.

کلیدواژه ها:

Hardened D-Latch circuit ، Carbon nanotubes transistors ، Transient faults ، Single Event Upset ، Critical charge