FPGA Implementation of 1024-bit Modular Processor For RSA Cryptosystem

In this paper, a hardware implementation of the RSA algorithm for public key cryptography is presented. The algorithm is dependent on the computation of modular exponentials. We have implemented our design on FPGA (Field Programmable Gate Array) and tested it. We used a Xilinx evaluation board as our FPGA target with 200000 typical gates. The ASIC technology we used is 0.25um. As a result, it is shown that the processor can perform 1024-bit RSA operation in less than 37ms at 60MHz.

کلیدواژه ها:

Cryptosystems ، RSA ، systolic array ، Montgomery algorithm ، modular multiplication ، modular exponentiation ، FPGA