Using of DTMOS Technique at 1-bit Full Adder Cells in Subthreshold Region

In this paper 1-bit full adder cells with different structures are simulated with 65nm, 90nm and 180nm CMOS technologies in the subthreshold region. DTMOS technique with connect body to gate is used in all of these full adder cells. The improvement values in delay and PDP are measured in all three technologies then these values are compared with each other.

کلیدواژه ها:

Full adder ، subthreshold ، DTMOS