PVT Analysis of an On-Chip Synchronous Elastic Data Pipeline Considering the Interconnect Effects in 16-nm Technology

In this paper, variability tolerance analysis for a synchronous elastic data pipeline is presented. In order to show communication tolerance of synchronous elastic circuits, all interconnect effects are considered and each interconnect part is matched with corresponding previous stage to achieve maximum performance. The proposed circuit is simulated using PTM 16-nm technology at 0.7 V power supply rail. The impact of Process, Voltage and Temperature (PVT) variations are considered to prove variability tolerance of the proposed scheme. In case of transistor width variation, 10% variation in 100 ◦C temperature is considered for the width of all transistors. Also, 10% variation is considered for the width, height and thickness of all interconnect parts in the 75 ◦C temperature. The simulation results shows that the pipeline delay in the synchronous elastic pipeline has 49.4% and 72.7% better tolerance to the transistor width and interconnect parameter variations comparing with synchronous counterpart, respectively. Also, considering 20% variation in the supply voltage, 21% better tolerance to this type of variation is obtained in case of synchronous elastic pipeline. Moreover, synchronous elastic pipeline tolerates 22.5% higher temperature with respect to the synchronous case.

کلیدواژه ها:

elastic pipeline ، variability ، delay uncertainty ، interconnect variation ، monte carlo analysis ، ptm 16-nm ،