From A 38 mW 12b 100 MS/s Pipelined ADC Design to Less Than a 20 mW One

A 12 bit pipelined ADC blocks are designed in 0.35 μm mixed-mode CMOS process. The final ADC conversion rate is 100 MS/s while the main circuits consumes only 38 mW power from a 3 V voltage supply. A wide swing gain-boosting technique, is used to design high dc gain and high unity gain bandwidth opamps. Also a technique is presented to reduce the power up to 20 mW.