Novel Asymmetric Gate Oxide Thickness Technology for Reduction of Gate Induced Drain Leakage Current in Nanoscale MOSFET Device for Low Power Applications

Gate Induced Drain Leakage (GIDL) current is one of the main leakage current components in MOSFET structure and plays an important role in data retention time of DRAM cells. GIDL can dominate the drain leakage current at zero bias and will limit the scalability of the MOSFET structure for low power applications. In this paper we propose a novel technique for reducing GIDL and hence off-state current in the nanoscale MOSFET structure. Proposed structure employs asymmetric gate oxide thickness which can reduce GIDL current an order of magnitude in comparison with the symmetric gate oxide thickness structure without sacrificing driving current.