A System-Level Verification Methodology Using Performance and Functional Assertions

As the designs get more complex, more sophisticated verification methodologies are required. At higher levels of abstraction, design and verification methodologies are required to minimize the cost of electronic product design. In this paper we integrate an assertion-based verification methodology with our objectoriented system-level synthesis methodology. Functional and performance assertions, based on Property Specification Language (PSL) and Logic of Constrains (LOC) are written during design process. Trace checkers are automatically generated to validate particular simulation runs or to analyze their performance characteristic(s). Following the case study, we demonstrate that the assertion-based verification is highly useful for both functional and performance system-level verification.

کلیدواژه ها:

System-Level Verification ، Assertion-Based Verification ، Performance Verification ، System-Level Design