Design and Implementation of a Configurable Real-Time FPGA-Based CA-CFAR Processor for Target Detection in Pulses Radar

Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present configurable hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The proposed architecture is based on an efficient procedure for FPGA implementation of the CA-CFAR detector. We have design our structure using VHDL language and implemented in spartan 6A starter kit, device.