Compact Hardware Architecture for Keccak Hash Function

Nowadays, cryptography is one of the mostimportant tools to ensure the safe delivery in mailing,electronic banking, and other sensitive digitalcommunication. Keccak hash algorithm which is finalwinner of SHA-3 hash algorithm competition is based on thesponge construction whose hardware performance is worthinvestigation.In this paper, we review kecccak and present a newarchitecture for its compact implementation. Our purposedmethod was coded in VHDL, and implementable on severalFPGAs and ASICs. This implementation was simulated onFPGAs, and ultimately this implementation is compared interms of consumer space with previous implementations

کلیدواژه ها:

Compact implementation ، Coprocessor ، FPGA ، KECCAK Hah Function ، SHA-3 ، VHDL