Compact Two-Stage CMOS Operational Amplifier with Enhanced Gain and Bandwidth via Cascode and Negative Capacitance Techniques

In this research, a two-stage CMOS amplifier has been developed, characterized by high gain, extensive frequency bandwidth, and a compact chip area. The design incorporates a negative capacitor unit, a flipped voltage follower, a cascode configuration in the first stage, and a small MOSFET-based capacitor. The use of negative capacitance effectively diminishes the parasitic capacitance from the previous stage, resulting in a notable improvement in gain bandwidth. The flipped voltage follower functions as a voltage buffer within the circuit and utilizes pole-zero cancellation techniques to improve frequency bandwidth. This design enhances the amplifier's performance by effectively managing stability and response characteristics. Additionally, modifications to the input stage of the operational amplifier through a cascode structure yield a significantly high-gain amplifier. The first stage's cascode arrangement for the MOSFET drivers, along with an active load that has high output resistance, accounts for the majority of the circuit's gain. By eliminating passive capacitors and substituting them with small MOSFET-based capacitors, the proposed design effectively reduces chip area while boosting gain bandwidth. The design and simulation processes were carried out using Cadence IC Design Virtuoso software based on standard TSMC ۰.۱۸ µm CMOS technology. The results indicate that the amplifier achieves a DC gain of ۸۰ dB, a bandwidth of ۱.۳ GHz, and a phase margin of ۸۴ degrees.

کلیدواژه ها:

Two-stage CMOS amplifier ، Flipped voltage follower ، Cascode structure ، Negative capacitance MOSCAP