Performance Evolution of Multi-Valued Nano Inverters

سال انتشار: 1405
نوع سند: مقاله ژورنالی
زبان: انگلیسی
مشاهده: 65

فایل این مقاله در 15 صفحه با فرمت PDF قابل دریافت می باشد

استخراج به نرم افزارهای پژوهشی:

لینک ثابت به این مقاله:

شناسه ملی سند علمی:

JR_CSTE-3-3_002

تاریخ نمایه سازی: 22 مهر 1405

چکیده مقاله:

In this paper, recent improvements of multi-valued inverters with focus on their superiority over conventional binary logic systems is investigated. The most concentration is on cutting edge transistors in order to utilize logic gates, with a focus on Carbon Nanotube Field Effect Transistors (CNTFET), and Graphene Nanoribbon Field Effect Transistors (GNRFET). The structural and operational principle of these emerging transistors are analyzed according to the comparative evaluation of their performance in terms of variety of parameters such as PDP, delay, power consumption and fabrication complexity. In this paper, the special attention is on CNTFET and GNRFET-based ternary and quaternary inverters. However, in order to have a better approach on performance of multi-valued inverters and the best candidate, pentarnary and binary inverters are investigated. The findings shows that the GNRFET-based inverters have lower propagation delay and less power consumption in comparison with CNTFET counterparts, despite certain trade-offs associated with increased power consumption in specific GNRFET implementations.

کلیدواژه ها:

نویسندگان

Sina Nabi

University of Science and Culture

Abdalhossein Rezai

University of Science and Culture, Bahar st, Shahid Qamushi st, Ashrafi Esfahani Bulvar

مراجع و منابع این مقاله:

لیست زیر مراجع و منابع استفاده شده در این مقاله را نمایش می دهد. این مراجع به صورت کاملا ماشینی و بر اساس هوش مصنوعی استخراج شده اند و لذا ممکن است دارای اشکالاتی باشند که به مرور زمان دقت استخراج این محتوا افزایش می یابد. مراجعی که مقالات مربوط به آنها در سیویلیکا نمایه شده و پیدا شده اند، به خود مقاله لینک شده اند :
  • S. Lin, Y.-B. Kim, and F. Lombardi, "CNTFET-based design of ...
  • M. H. Moaiyeri, K. Navi, and O. Hashemipour, "Design and ...
  • H. Lee, S. Kim, J. Kim, J. Jeong, J. Yang, ...
  • S. Tabrizchi, F. Sharifi, A.-H. Badawy, and Z. Saifullah, "Enabling ...
  • G. E. Moore, "Cramming more components onto integrated circuits," ed: ...
  • K. C. Smith, "A multiple valued logic: a tutorial and ...
  • Hurst, "Multiple-valued logic—Its status and its future," IEEE Transactions on ...
  • F. Sharifi, M. H. Moaiyeri, K. Navi, and N. Bagherzadeh, ...
  • E. Dubrova, "Multiple-valued logic in VLSI: challenges and opportunities," in ...
  • A. Raychowdhury and K. Roy, "Carbon-nanotube-based voltage-mode multiple-valued logic design," ...
  • F. Zahoor et al., "Design implementations of ternary logic systems: ...
  • Y. Yasuda, Y. Tokuda, S. Zaima, K. Pak, T. Nakamura, ...
  • M. H. Moaiyeri, R. F. Mirzaee, A. Doostaregan, K. Navi, ...
  • T. Araki, H. Tatsumi, M. Mukaidono, and F. Yamamoto, "Minimization ...
  • J. T. Butler and H. G. Kerkhoff, "Multiple-valued CCD circuits," ...
  • S. Onneweer, H. Kerkhoff, and J. Butler, "Structural computer-aided design ...
  • F. Pelayo, A. Prieto, A. Lloris, and J. Ortega, "CMOS ...
  • M. Heydari, A. Rezai, and F. Javaheri, "Design of Novel ...
  • M. Balali, A. Rezai, H. Balali, F. Rabiei, and S. ...
  • A. Karimi and A. Rezai, "High‐performance digital logic implementation approach ...
  • A. Amirany, K. Jafari, and M. H. Moaiyeri, "BVA-NQSL: A ...
  • M. BahmanAbadi, A. Amirany, M. H. Moaiyeri, and K. Jafari, ...
  • S. Nabi and A. Rezai, "Performance analysis of FET-based Universal ...
  • A. Karimi and A. Rezai, "A design methodology to optimize ...
  • M. Shafizadeh and A. Rezai, "Improved device performance in a ...
  • B. D. Madhuri and S. Sunithamani, "Design of ternary logic ...
  • P. Gowrisankar, "Design of multi-valued ternary logic gates based on ...
  • S. Karmakar, J. A. Chandy, and F. C. Jain, "Design ...
  • S. S. Dan and S. Mahapatra, "Impact of energy quantisation ...
  • J. Appenzeller, "Carbon nanotubes for high-performance electronics—Progress and prospect," Proceedings ...
  • A. Hazeghi, T. Krishnamohan, and H.-S. P. Wong, "Schottky-barrier carbon ...
  • A. Naderi and M. Ghodrati, "An efficient structure for T-CNTFETs ...
  • V. Prasad and D. Das, "A review on MOSFET-Like CNTFETs," ...
  • S. J. Basha and P. Venkatramana, "High performance quaternary logic ...
  • M. Nayeri, P. Keshavarzian, and M. Nayeri, "Approach for MVL ...
  • X. Wang and H. Dai, "Etching and narrowing of graphene ...
  • M. Khandelwal and N. Sharan, "Design and performance comparison of ...
  • G. Singh, M. Kaur, and Y. Kumar, "CNTFET for Logic ...
  • E. Abbasian, S. Sofimowloodi, and A. Sachdeva, "Highly-efficient CNTFET-based unbalanced ...
  • M. H. Moaiyeri, A. Doostaregan, and K. Navi, "Design of ...
  • H. Samadi, A. Shahhoseini, and F. Aghaei-liavali, "A new method ...
  • K. J. Krishna, S. R. Kumar, J. S. P. Dharshini, ...
  • S. RatanKumar, L. K. Rao, and M. K. Kumar, "Design ...
  • S. A. Ebrahimi, M. R. Reshadinezhad, A. Bohlooli, and M. ...
  • Z. T. Sandhie, F. U. Ahmed, and M. H. Chowdhury, ...
  • K. Mahesh and S. Shameem, "High-speed and power-efficient ternary logic ...
  • M. K. Majumder, N. R. Kukkam, and B. K. Kaushik, ...
  • G. S. Simate, S. E. Iyuke, S. Ndlovu, C. S. ...
  • J. Banothu, "Design of High-Speed GNRFET Based Ternary Logic Circuits," ...
  • Z. T. Sandhie, F. U. Ahmed, and M. Chowdhury, "GNRFET ...
  • D. G. Anil, Y. Bai, and Y. Choi, "Performance evaluation ...
  • نمایش کامل مراجع