Analysis of the design method of half adder and full adder

The word RISC is simplified or an abbreviation of Reduced instruction set computing meaning 'simplified instruction set' or 'optimized instruction set'. Risk is one of the processor designs that is designed based on simplifying and optimizing the set of instructions, and in other words, instead of processing a set of complex instructions, it uses much simpler and more optimal instructions for processing, which results in much more optimal efficiency and performance. it will be Risk uses a pipeline method for processing. Around ۱۹۸۰, the theory of designing and building low-order computers, known as RISC computers, became widespread and accepted by computer scientists. It was agreed that inside the ALUs, only the adder circuit should be designed and implemented in terms of hardware, and other arithmetic operations should be performed by the addition operation and some auxiliary operations with special methods and different algorithms. For this reason, after many efforts, scientists were able to implement new actions such as Shift and Complement types, with the help of arithmetic addition, to perform other actions on the computer if needed. Due to the mentioned reasons, arithmetic addition operation is the only computing hardware operation that is designed and implemented in terms of hardware in ALU. In this article, an attempt has been made to review the process of design, implementation and development of various types of combined and sequential adders in computer systems.

کلیدواژه ها:

Multiplexer ، serial adder ، half adder ، full adder ، ۴-bit adder and subtracter