Enhancing VLSI placement efficiency through comprehensive parameter optimization and cutting-edge techniques for superior design quality

The process of placement, which involves determining the spatial coordinates of numerous standard cells and macros, is a critical and labor-intensive stage in contemporary Very Large-Scale Integration (VLSI) physical design. The placement of components in a circuit has long been challenging due to the increasing complexity of structures and the continuous advancements in VLSI manufacturing techniques. This research introduces a Reinforcement Learning (RL) strategy known as the Reinforcement Learning Parameter Optimization Model (RLPOM) and a Graph Neural Network (GNN) to formulate the parameter optimization problem as a RL task. The agent is trained exclusively using RL through a self-search approach. The selection of the RL algorithm is motivated by the need to address the challenges posed by data sparsity and latency in placement runs. The mean outcomes of the proposed RLPOM across all performance measures are as follows: The measured parameters for the system under study include wire length (۱۳.۷۱ um), congestion (۴.۵%), area utilization (۸۲.۴%), run time (۲۶.۶۸ sec), power consumption (۱۵.۵۷ W). This approach leverages the natural advantages of GNN and RL to achieve superior global placement, which is unique to the best of our knowledge.

کلیدواژه ها:

Placement ، Very large-scale integration ، Reinforcement Learning ، Electronic Design Automation ، Self-Search Approach