Design of ۶۵ nm ۶T SRAM using improved sense amplifiers and write driver circuits

Designing high-speed ۶T SRAM for efficient read and write operations poses a significant challenge for circuit designers. In this paper, we propose a ۶۵ nm ۶T SRAM architecture using sense amplifiers and write driver circuits to enhance the read and write performance. The sense amplifier helps the reading process go faster and the reading data be more stable. The write driver is designed with a symmetrical structure to reduce the write delay. In addition, the control circuit performs the checking process to synchronize read operations, optimize latency without interruption. The simulation result shows that the read delay and write delay are ۵۸.۶۶ ps and ۷۹.۶۷ ps, respectively. These delays outperform most of the other study.

کلیدواژه ها:

Static random-access memory ، Sense amplifier ، Write driver circuit ، Complementary metal oxide semiconductor ، ۶۵ nm