A CMOS ۶۵ nm on-chip RF inductor with hybrid spiral-meander layout optimization and ferroelectric stack-up integration for Q-factor enhancement

On-chip inductors are crucial for enhancing the functionality of microelectronic devices, particularly in wireless communication. Still, traditional designs often lead to increased chip size and reduced performance due to their bulkiness and integration challenges. By utilizing an electromagnetic (EM) simulation tool, this research presents a novel on-chip inductor design optimized for ۶۵ nm CMOS technology, achieving an inductance of ۳.۲ nH with a Q-factor of ۱۵.۳۱ at ۱.۷ GHz. The primary contributor to the Q-factor enhancement is the layout optimization techniques, which improve the Q-factor by approximately ۲۱%. Additionally, further improvements in inductance and Q-factor are achieved by integrating Nickel Zinc Cobalt-based ferroelectric liquid materials into the simulation stack-up layer. This material stack-up serves as a secondary contributor, enhancing the magnetic properties of the inductor and increasing the Q-factor to ۱۵.۸۳ whichis an additional ۶% improvement over the proposed design. The proposed layout optimization and material innovations demonstrate the potential for achieving higher inductance values and Q-factors, effectively addressing the limitations of conventional methods. The results highlight the feasibility of incorporating advanced materials in on-chip inductor design, paving the way for next-generation RF integrated circuits that meet the growing demands for miniaturization and energy efficiency in modern electronics.

کلیدواژه ها:

Complementary metal oxide semiconductor ، Inductor ، Quality Factor ، Layout optimization ، ferroelectric