Novel Designs of Nanometric Parity Preserving Reversible Circuits
محل انتشار: همایش مهندسی کامپیوتر و توسعه پایدار با محوریت شبکه های کامپیوتری، مدلسازی و امنیت سیستم ها
سال انتشار: 1392
نوع سند: مقاله کنفرانسی
زبان: انگلیسی
مشاهده: 1,454
فایل این مقاله در 8 صفحه با فرمت PDF قابل دریافت می باشد
- صدور گواهی نمایه سازی
- من نویسنده این مقاله هستم
استخراج به نرم افزارهای پژوهشی:
شناسه ملی سند علمی:
CESD01_012
تاریخ نمایه سازی: 25 اسفند 1392
چکیده مقاله:
Power consumption is one of the important issues in VLSI design. Reversible logic produces zero power; therefore, nowadays researchers attend to it in order to optimize power. In the digital systems, one of the methods of achieving to fault tolerance is parity preserving. This paper proposes a new parity preserving reversible gate, PPRG. The most significant aspect of the PPRG gate is that it can be used to produce parity preserving reversible full adder circuit. This circuit is more efficient than the existing designs in term of quantum cost and it is optimized in terms of number of constant inputs and garbage outputs. A novel parity preserving reversible 4:2 compressor is also proposed using the PPRG gate. It is the first attempt to design parity preserving reversible 4:2 compressor. Thus, this paper is the good initiator for building more complex parity preserving reversible circuits.
کلیدواژه ها:
نویسندگان
Soghra Shoaei
۱Department of Computer Engineering, Tabriz Branch, Islamic Azad University, Tabriz, Iran
Majid Haghparast
۲Department of Computer Engineering, Shahre-Rey Branch, Islamic Azad University, Tehran, Iran