A nano-design of an ultra-efficient and fault-tolerant decoder based on quantum-dots

In the field of electronics, which is known as digital electronics, all devices consume high energy to generate correct output. Analog electronics, on the other hand, operate primarily with analog signals to generate output. Despite the name, analog design considerations are a significant part of digital electronics designs. Digital electronic circuits are composed of large assemblies of logic gates, which are often found in electronic circuits. Complex devices have simple electrical representations of Boolean logic functions. On the other hand, in digital electronics, a decoder is one of the extraordinary circuits that can be an essential part of any microprocessor. It is a combinational circuit, which means its output depends on its present inputs. It generates several output lines by enabling one input line. Multiple communication projects between two devices involve the use of decoders. However, in these circuits, vulnerability to fault, low speed, low accuracy, and high occupied area are considered the notable challenges; consequently, with the help of new technologies like quantum dot, all issues can be solved. One of the best options for nanoscale technologies is quantum-dot automation (QCA), which has special qualities that include extremely low occupancy and power consumption. Since QCA technologies offer possible advantages over CMOS and other transistor-based technologies, such as smaller occupied area, low energy dissipation, and fast speed, they can be employed in arithmetic logic units for microprocessors. In this paper, a fault-tolerant (FT) ۱:۲ decoder is designed using a majority gate. Then, an FT version of the ۲:۴ decoder is suggested based on the ۱:۲ decoder. The simulation results are provided to confirm the correctness of the suggested designs.

کلیدواژه ها:

Circuit Design ، Nanotechnology ، Decoder ، Subtractor ، Quantum-dot Cellular Automata