DESIGNING A RECONFIGURABLE ACCELERATOR

Many of the video processing algorithms cannot be implemented in real time on general computers, due to their computational complexity. For an efficient implementation, a custom hardware that can be reconfigured for the algorithm, is used. In this paper a new acceleration hardware based on FPGA elements is proposed. This hardware can be adapted with the processing algorithm through FPGA design reconfiguration. Using a PCI slot, this hardware communicates with a Pc. The FPGAs are programmed through the PCI slot. The video frames are supplied to this hardware for processing. The performance of this hardware is evaluated using warping algorithms. The first and second order warping for a ۵۱۲*۵۱۲ frame can be done in ۷.۹ ms.

کلیدواژه ها:

FPGA ، FPGA ، ACCELERATOR ، REAL-TIME IMPLEMENTATION ، IMAGE WARPING ، تسریع کننده ، نگاشت تصویر ، پیاده سازی بی درنگ