Exploring the Design Space for Area-Efficient Embedded VLIW Packet Processing Engine

Today area-efficiency is an important factor in designing embedded systems. This paper presents a design space exploration based on an embedded VLIW processor forfinding out the optimum architecture for ever increasing demands of embedded packet-processing applications. In ourexploration, we use the VEX toolchain for exploring the effects of memory hierarchy, different architectural configurations, and compiler optimizations on both performance and area.Exploration results will find out the best architecture and compiler optimizations for VLIW embedded packetprocessing engines to have area-efficiency as well as timeefficiency.

کلیدواژه ها:

VLIW instruction-level parallelism ، Design space exploration ، Area-efficient embedded architecture