A ۰.۴V, ۷۹۰µW CMOS low noise amplifier in sub-threshold region at ۱.۵GHz

A fully integrated low-noise amplifier (LNA) with ۰.۴V supply voltage and ultra low power consumption at ۱.۵GHz by folded cascode structure is presented. The proposed LNA is designed in a TSMC ۰.۱۸ µm CMOS technology, in which all transistors are biased in sub-threshold region. Through the use of  proposed circuit for gain enhancement in this structure and using forward body bias technique, a very high figure of merit is achieved, in comparison to similar structures. The LNA provides a power gain of ۱۴.۷dB with a noise figure of ۲.۹dB while consuming only ۷۹۰µW dc power. Also, impedance matching of input and output of the circuit in its operating frequency is desirable and in the whole bandwidth of the circuit, input and output isolation is below -۳۳dB.

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