Implementation of RADAR Quadrature Channel Receiver in FPGA

in this paper we have presented the implementation of radar digital quadrature channel receivers in FPGA. Utilizing direct digitalization due to avoid improbable matching in producing in-phase (I) and quadrature (Q) signals, is greatly respecting in every modern system but this merit needs some considerations which are highlighted in the current paper. Two factors resource and maximum frequency for hardware implementation of proposed algorithm utilizing Virtex-۵ ML۵۰۶ are evaluated and compared with the customary algorithm of analog and digital receivers which generally utilize two mixers, lowpass filters and analog to digital converters for down converting signal from intermediate frequency to baseband. Also in this paper some simulations for different examples are illustrated

کلیدواژه ها:

radar ، en ، digital quadrature channel receiver ، FPGA ، IF sampling