An FPGA-based partitioned word voter for a TMR system

In designing many systems, fault tolerance is a critical requirement for decreasing the effects of thetransient faults; in this regard, a Triple Modular Redundancy (TMR) is a highlighted technique. The voteris an essential component of TMR. As the effects of the faults mask in a bit-by-bit voter, some multipletransient faults are not tolerated. In this paper, a novel ۳-bit-partitioned word voter has been implementedby six-input lookup-tables (LUT-۶) of FPGAs, and then an n-bit TMR system is proposed. Practicalexperiments show that the proposed voter enhances the data integrity and reduces the decision latencycompared to the previous voters

کلیدواژه ها:

FPGA ، Lookup Table (LUT) ، Triple Modular Redundancy (TMR) ، Fault tolerance ، Voter.