Challenges in ASIC design of cryptography algorithms

This paper work on implementing BMWcryptographic hash algorithm as one of the algorithms usedin chained cryptographic algorithms like LYRA۲. For theimplementation both SOC and also ASIC designimplementation of the algorithm is considered. For SOCimplementation Zynq devices are used. ZC۷۰۶ board asone of the famous evaluation boards is considered andselected in Vivado software for the implementation.Design-vision ASIC synthesizer is used for mapping theHDL code to the standard cells. Also cadence encountertool is used for extracting the layout of the final designedmapped output of the design-vision. The maximumachievable clock frequency of the design is ۱۳MHz fromSOC implementation and ۳۵.۷۱ MHz from ASICimplementation. The total area of the ASIC design in ۴۵nm CMOS technology is ۴۲۰*۴۲۰ (μm۲). The throughputof the design is also ۱۳۳۱ and ۳۶۵۷ Mbps for SOC andASIC design implementation respectively.

کلیدواژه ها:

BMW ، hash function ، cryptocurrency ، SOC ، ASIC ، Zynq.