Efficient hardware accelerator design for Skein cryptography algorithm

Nowadays, there has been an increasing demand in cryptocurrency popularity. As an example of an ASIC-resistant hashing algorithm Lyra۲REv۲ and basically Skein algorithm as one of the main hashing blocks of that is considered in this paper. FPGAs are low risk, cost efficient hardware for implementing the ASIC resistance hashing algorithms. In this paper by software/hardware portioning, different parameters of hardware design including power, efficiency and resource utilization have been improved. The clock frequency and hash rate of the design is ۱۴۰ MHz and ۱۴ respectively.

کلیدواژه ها:

Skein algorithm ، digital design ، SOC ، Zynq.