Design and evaluation of energy efficient and low leakage logic gates by using GDI and SR-Latch structures

Abstract: This study presents an effective family of logic gates such as NAND, XOR and NOR circuits based on CMOS technology, Gate Diffusion Input (GDI) cell and Swing restoration buffers (SR-Latch). The pull down network of proposed designs including double pass-transistor logic (DPL). This method greatly resolves problems caused by the circuits output swing. The SR-Latch buffers of the pull up network of proposed designs drive the output nodes of the logic gate and reducing propagation delay and leakage current. In fact, we proposed the new combination of GDI cell and SR-Latch buffers which improved the output swing, leakage current, propagation delay, total energy consumption and the Power Delay Product (PDP) in comparison with traditional GDI and GDI-SR cells. Also, the Voltage Transmission Characteristic (VTC) and noise margin of circuits is presented. Monte-Carlo simulation results showed that the proposed XOR, NAND and NOR designs have better performance against previous works.

کلیدواژه ها:

_GDI ، SR-Latch ، logic gates ، Monte-Carlo