A Novel Method Design Multiplexer Quaternary with CNTFET

سال انتشار: 1399
نوع سند: مقاله ژورنالی
زبان: انگلیسی
مشاهده: 284

فایل این مقاله در 10 صفحه با فرمت PDF قابل دریافت می باشد

استخراج به نرم افزارهای پژوهشی:

لینک ثابت به این مقاله:

شناسه ملی سند علمی:

JR_JECEI-8-1_002

تاریخ نمایه سازی: 23 آذر 1399

چکیده مقاله:

Background and Objectives: In recent decades, due to the effect of the short channel, the use of CMOS transistors in the nanoscale has become a major concern. One option to deal with this issue is the use of nano-transistors. Methods: Using nano-transistors and multi-valued logic (MVL) can reduce the level of chips and connections and have a direct impact on power consumption. The present study reports the design of a new method of Multiplexers (MUXs) based on quaternary logic and transistors of carbon nanotubes (CNTFET) and having a new look at the layout and use of MUXs. Results:The use of special rotary functions and unary operators in Quaternary logic in the design of MUXs reduced the number of CNTFETs from 27% to 54%. Also, the use of MUXs in the Adder structure resulted in a 54% reduction in Power Delay Product (PDP) and a 17.5% to 85.6% reduction in CNTFET counts. Conclusion: The simulated results display a significant improvement in the fabrication of Adders, average power consumption, speed, and PDP compared to the current best-performing techniques in the literature. The proposed operators and circuits were evaluated under various operating conditions. The results show the stability of the proposed circuits.

نویسندگان

S. Rahmati

Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran

E. Farshidi

Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran

J. Ganji

Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran

مراجع و منابع این مقاله:

لیست زیر مراجع و منابع استفاده شده در این مقاله را نمایش می دهد. این مراجع به صورت کاملا ماشینی و بر اساس هوش مصنوعی استخراج شده اند و لذا ممکن است دارای اشکالاتی باشند که به مرور زمان دقت استخراج این محتوا افزایش می یابد. مراجعی که مقالات مربوط به آنها در سیویلیکا نمایه شده و پیدا شده اند، به خود مقاله لینک شده اند :
  • [1] S. Iijima, "Helical microtubules of graphitic carbon," Nature, 354(6348): ...
  • [2] G. E. Moore, "Cramming more components onto integrated circuits,” ...
  • [3]J. Guo, S. O. Koswatta, N. Neophytou, M. Lundstrom, "Carbon ...
  • [4] T. Temel, A. Morgul, "Implementation of multi-valued logic gates ...
  • [5] A. N. Gupte,  A. K. Goel, "Study of quaternary ...
  • [6] F. Sharifi, M. H. Moaiyeri, K. Navi, "A novel ...
  • [7] E. Abiri, A. Darabi, S. Salem, "Design of multiple-valued ...
  • [8] D. Das, A. Banerjee, V. Prasad, "Design of ternary ...
  • [9] K. Vasundara Patel, K. Gurumurthy, "Design of high-performance quaternary ...
  • [10] C. Vudadha, A. Surya, S. Agrawal, M. Srinivas, "Synthesis ...
  • [11] S. Lin, Y.B.  Kim, F. Lombardi, “CNTFET-based design of ...
  • [12] S. A. Ebrahimi, M. R. Reshadinezhad, A. Bohlooli, M. ...
  • [13] F. Sharifi, M. H. Moaiyeri, K. Navi, N. Bagherzadeh, ...
  • [14] E. Roosta, S. A. Hosseini, "A Novel Multiplexer-Based Quaternary ...
  • [15] B. Srinivasu, K. Sridharan, "Carbon nanotube FET-based low-delay and ...
  • [16] M. H. Moaiyeri, M. Nasiri, N. Khastoo, "An efficient ...
  • [17] M. H. Moaiyeri, K. Navi, O. Hashemipour, "Design and ...
  • [18]J. Deng and H.-S. P. Wong, "A compact SPICE model ...
  •  [19] A. Daraei, S.A. Hosseini, Novel energy-efficient and high-noise margin ...
  • [20] S. Fakhari, N. Hajizadeh Bastani , M.H. Moaiyeri, “A ...
  • [21]J. Deng, "Device modeling and circuit performance evaluation for nanoscale ...
  • نمایش کامل مراجع