Multi Parametric Optimized Architectural Synthesis of an Application Specific Processor

  • سال انتشار: 1388
  • محل انتشار: چهاردهمین کنفرانس بین المللی سالانه انجمن کامپیوتر ایران
  • کد COI اختصاصی: CSICC14_025
  • زبان مقاله: انگلیسی
  • تعداد مشاهده: 1729
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نویسندگان

Summit Sehgal

Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada

Sedaghat

Ryerson University/Department of Electrical and Computer Engineering, Toronto, Canada

Anirban Sengupta

Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada

Zhipeng Zeng

Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada

چکیده

Recent advancements in the field of multimedia and wireless communications have led to a wide array of application and services requiring high data processing rate at minimal power consumption. This new generation of data hungry portable devices requires power efficient hardware solutions where the operational specifications are as important as objective functionality. Conventional processing solutions like MIPS fall short on real time computational intensive operations due to large software overhead. This class of applications demands dedicated hardware units like pplication Specific Processors (ASP) working as hardware accelerators for intensive data processing operations. In this paper we describe a novel Register Transfer Level (RTL) synthesis process of a power and throughput optimized ASP for a sample application. The ASP implemented on an FPGA, can serve as a hardware accelerator for system on chip (SOC) or as a standalone Application Specific Integrated Circuit (ASIC) at silicon level.

کلیدواژه ها

Application Specific Processor; Register Transfer Level; High Performance Design; Scheduling; Binding; Control and Data path

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