S.S Ghoreishi - Dept. of Electrical Engineering, Islamic Azad University (IAU), Science and Research Branch, Tehran, Iran
M.A pourmina - Dept. of Electrical Engineering, Islamic Azad University (IAU), Science and Research Branch, Tehran, Iran
H Bozorgi - The University of Guilan / Dept. Of Electronics, Rasht, Iran

Since for most public-key cryptosystem like Rivest, Shamir, and Adelman (RSA), the ElGamal signature scheme , and the Diffe-Hellman key exchange or the Digital Signature Algorithm (DSA), modular reduction is requested, so it is desirable to implement modular reduction for the high speed performance. In this paper, we present new hardware architecture for a high-speed implementation of the modular reduction algorithm on an FPGA (Field Programmable Gate Array) platform. In this way, first we explained an algorithm for computing the residue. We have implemented our design on FPGA platform. We used Xilinx VirtexII and XC4000 families. Also VHDL codes dealing with this structure and synthesized results have been presented. As a result it is shown that we can calculate the residue where and are 1024- bit integers, using a clock rate of 113.9 and 39.3 MHz on Xilinx VirtexII and XC4000 series FPGAs, respectively . This architecture could be used for high speed implementation of the RSA public- key cryptosystem.

Modular Reduction; Sign estimation; CSA; FPGA; Public Key