Modeling of Feedback Pulse Jitter Effects on Sigma-Delta Modulator

A proposed system level jitter implementation is developed in MATLAB-Simulink to analyze the effects of the feedback jitter on the sigma-delta modulator SNR degradation. Based on the proposed models; also, the tolerable amount of jitter in Continuous-Time Sigma-Delta Modulators are investigated. Two types of rectangular feedback pulse wave, Return to Zero (RZ) and Non-Return to Zero (NRZ) are manipulated with a made up jitter and impose to the different conventional high-order configurations to evaluate the effect of topologies on In-Band Noise. Simulation results confirm that the loop filter with the zeros location optimization result in more than 6dB improvement in clock jitter sensitivity with RZ-DAC. All of the simulations are system level and done in MATLAB-Simulink.

کلیدواژه ها:

sigma-delta ، continuous-time ، pulse-jitter