A 32-bit pipeline phase accumulator with clock division technique at 0.5μm CMOS technology

In this paper, a low-power 32-bit pipeline accumulator based on novel technique for design of phase accumulator (PA) by connecting blocks of the carry-lookahead adder (CLA) in each pipeline stage and D-type flip flop (D-FF) for 250 MHz is presented. The proposed PA exploits the advantage of carry-lookahead adder, TSPC D-FF and clock division method to decrease the area, and therefore the area is reduced to 14.64% of a conventional pipeline accumulator. The design development of 32-bit PA blocks has completed using HSPICE software and Virtouso Tools in Cadence. The proposed accumulator developed by CSMC 0.5μm CMOS technology. The power consumption of proposed pipelined accumulator with supply voltage of 5 V is 60 mW. The total area of the designed chip is 673μm × 441μm.

کلیدواژه ها:

direct digital frequency synthesizer (DDFS) ، carry-lookahead adder (CLA) ، phase accumulator (PA) ، clock division