Seyyed Reza Talebiyan - Department of Electronic Engineering, Imam Reza International University , Mashhad, Iran
Milad Jalalian Abbasi Morad - Department of Electronic Engineering, Imam Reza International University , Mashhad, Iran
Ebrahim Pakniyat - Department of Electronic Engineering, Imam Reza International University , Mashhad, Iran

This paper, presents a new design for 1-bit full adder cell using hybrid-CMOS logic style. The new full swing full adder cell has excellent performance in low values of power supply, so this circuit is a suitable choice for low-power applications and low-voltage designs. According to the simulation results, the proposed full adder has the best power consumption, propagation delay and power-delay product compared to its counterparts, such that the power-delay product of the proposed full adder is 39% better than the next best PDP. HSPICE simulations using TSMC's 130nm technology with a power supply of 1.2V was utilized to evaluate the performance of the circuits.

Full Adder, High-Performance, Hybrid-CMOS, Low-Power, Low-Voltage, VLSI