Arash Ahmadi - Electronic System Design Group, School of Electronics and Computer Science, University of Southampton
Mark Zwolinski - Electronic System Design Group, School of Electronics and Computer Science, University of Southampton

From high level synthesis point of view, target design can be divided into two parts: controller and datapath. Single shared bus is a suitable structure for datapath synthesis regarding interconnections costs which suffers from several drawbacks such as its low data communication bandwidth. It has also been shown that the wordlength of functional units has a great impact on design costs. A combination of both methods is the core idea of this paper which is offering an improved communication structure. In this method datapath is partitioned into groups connected to segmented shared buses and every partition has a different width and all the functional units connected to a bus partition have the same input/output word-lengths. Having controlled the group binding and word-length of the functional units, as well as the other synthesis parameters, a high-level synthesis tool is introduced to implement DSP algorithms in digital hardware. The tool uses a multi-objective optimization genetic algorithm to minimize the circuit area, delay, power consumption and digital noise by selecting optimal grouping and word-length for the shared bus structure. Results demonstrate that savings can be made in the overall system costs by applying this method.

High Level Synthesis, Bus Partitioning, Communication Synthesis, System Bus, Word-Length optimization.