Amin Moradhasel - School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran
Babak Nadjar Araabi - School of Electrical and Computer Engineering, College of Engineering, University of Tehran School of Cognitive Sciences, Institute for Research
Mehdi Fakhraie - School of Electrical and Computer Engineering, College of Engineering, University of Tehran
Majid Nili Ahmadabadi - School of Electrical and Computer Engineering, College of Engineering, University of Tehran School of Cognitive Sciences, Institute for Research

Saliency map is a central part of many visual attentionsystems, particularly during learning and control of bottom-upattention. In this research we developed a hardware tool toextract saliency map from a video sequence. Saliency map isobtained by aggregating primary features of each frame, such asintensity, color, and lines orientation, along with temporaldifference. The system is designed to provide both high speed andacceptable accuracy for real-time applications, such as machinevision and robotics. A versatile Verilog model for realization ofthe video processing system is developed, which can easily bemapped and synthesized on various FPGA or ASIC platforms.The proposed parallel hardware can process over 50 millionpixels in a second, which is about 2x faster than the state-of-theartdesigns. Experimental results on sample images justify theapplicability and efficiency of the developed system in real-timeapplications.

saliency map; parallel hardware system; visual attention; video processing