Yusof Doost Hoseini - Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan ۸۴۱۵۶-۸۳۱۱۱, Iran
Sayed Masoud Sayedi
Saeid Sadri

A novel CMOS image sensor architecture for computing integral image is presented. The proposed circuit reads the image and produces the integral imagesimultaneously. In the circuit, the image is divided into vertical blocks and integral images of the blocks are computed in parallel. The final integral image is producedusing an updating method. To evaluate the performance of the circuit the blob detector implemented in Speeded UpRobust Features (SURF) algorithm is used. In comparison with conventional sequential method, while the final results are similar, the proposed approach is 500 times faster in capturing the integral image of a 160×160 sample image

Integral image, Hardware implementation, CMOS image sensor, Parallel Computation